1. Field of the Invention
The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device comprising a memory cell array having a plurality of memory cells disposed in a row direction and a column direction, each memory cell having a floating gate formed between a channel area and a control gate via an insulation film. Particularly, the present invention relates to a method of programming into a memory cell array of a multilevel nonvolatile semiconductor memory device capable of storing data of three or more levels in each memory cell.
2. Description of the Related Art
Conventionally, an ETOX (EPROM Thin Oxide; a registered trademark of Intel Corporation) type flash memory is a most general flash memory among the above kind of nonvolatile semiconductor memory device.
FIGS. 3A and 3B are a schematic cross-sectional view and an equivalent circuit diagram respectively of a memory cell transistor that constitutes a memory cell of the ETOX type flash memory. As shown in FIGS. 3A and 3B, a floating gate 40 is formed as a charge storage area over a channel area 41 between a source 45 and a drain 46 via a tunnel oxide film 43. A control gate 42 is formed over the floating gate 40 via an inter-layer insulation film 44.
The principle of operation of the ETOX type flash memory cell will be explained. To program data into the memory cell, Vpp (for example, 9 V) is applied to the control gate, a reference voltage Vss (for example, 0 V) is applied to the source, and Vdp (for example, 5 V) is applied to the drain. Based on this arrangement, a large amount of current flows in the channel area between the source and the drain. A number of hot electrons are generated in a portion of the channel area with high electric field near the drain, and the electrons are injected into the floating gate, thereby increasing the threshold voltage of the memory cell. For a memory cell into which no data is programmed, 0 V is applied to the drain, or the drain is set open or floating.
To erase data from the memory cell into which the data is programmed, Vnn (for example, −9 V) is applied to the control gate, Vpe (for example, 6 V) is applied to the source, and the drain is set open or floating. In this state, electrons are extracted from the floating gate near the source via the tunnel oxide film, thereby lowering the threshold voltage of the memory cell. According to this source erasing system, a BTBT (Band To Band Tunneling) current flows between the source and a semiconductor substrate. Of the hot holes and hot electrons that are generated simultaneously with the occurrence of the BTBT current, some of the hot holes are attracted to the tunnel oxide film, and are trapped within the tunnel oxide film. This phenomenon of the trapping of hot holes within the tunnel oxide film is known to degrade the data retention and endurance properties of the memory cell. Another drawback of this BTBT Erase Scheme is the relatively high erase current required from an internally generated high-voltage charge pump circuit. A channel erasing system is available as one of improved erasing methods. According to this channel erasing system, Vnn (for example, −9 V) is applied to the control gate, Vpe (for example, 5V) is applied to the substrate, and the source and the drain are set open or floating. In this state, electrons are extracted from the floating gate via the tunnel oxide film, thereby lowering the threshold voltage without the concerns of trapping of hot holes and high erase current requirement.
In the actual flash memory, a memory cell does not exist as a single unit. As shown in FIG. 2, a plurality of memory cells are arranged in an array to structure a memory cell array. Control gates of a plurality (n+1, in FIG. 2) of flash memory cells are connected to word lines (WL0 to WLn). Drains of a plurality (m+1, in FIG. 2) of flash memory cells are connected to bit lines (BL0 to BLm). As a result, the memory cell array shown in FIG. 2 has (n+1)×(m+1) flash memory cells. The memory cell array consisting of the plurality of memory cells has a mixture of memory cells having different threshold voltages representing the data stored. Therefore, these threshold voltages have distributions corresponding to the number of memory cells.
FIG. 15 is an illustration of a state of the threshold voltages of a conventional nonvolatile memory. In other words, FIG. 15 illustrates distributions of the threshold voltages in the memory cells for the memory cell array having the plurality of flash memory cells disposed. The horizontal axis represents threshold voltages in the memory cells, and the vertical axis represents numbers of memory cells within the memory cell array having the threshold voltages represented by the horizontal axis. Usually, in the binary flash memory, a state that electrons are injected into the floating gate of the memory cell is a data programming state. Data “0” represents this state. A state that electrons are extracted from the floating gate of the memory cell is a data erasing state. Data “1” represents this state. When the threshold voltage in the memory cell increases and exceeds a predetermined voltage (for example, 5 V) based on the data program operation, the data program operation ends, as shown in FIG. 15. When the threshold voltage in the memory cell decreases and becomes lower than a predetermined voltage (for example, 3 V) based on the data erase operation, the data erase operation ends. When the threshold voltages in the memory cells belong to either one of the two ranges of threshold voltages shown in FIG. 15, two states (i.e., a memory state) can be identified with one flash memory cell.
To read the memory state of the memory cell, Vdr (for example, 1 V) is applied to the drain, and Vgr (for example, 5 V) is applied to the control gate. For example, when a threshold voltage is in the data erasing state and also when the threshold voltage is low, a current flows through the memory cell. It is decided that the data “1” represents this state. On the other hand, when a threshold voltage is in the data programming state and also when the threshold voltage is high, a current does not flow through the memory cell. It is decided that the data “0” represents this state. These decisions are made by detecting and comparing a current that flows through the memory cell from which data is to be read in the memory cell array and a current that flows through a reference cell which is set to a predetermined reference voltage.
In the program operation sequence of the ETOX type flash memory, the following program verification is carried out. At a reading step of verifying whether a threshold voltage reaches a desired range of threshold voltage, that is, whether the data is programmed normally, Vgv (for example, V) is applied to the control gate, and Vdv (for example, 1 V) is applied to the drain. With this arrangement, the threshold voltage is read, and is compared with a predetermined reference voltage.
In the ETOX type flash memory, a multilevel memory larger than one bit (i.e., binary) can be realized with one memory cell, based on a provision of three or more areas of threshold voltage range. FIG. 4 is a schematic illustration of one example of threshold voltage distributions of memory cells in a four-level flash memory. As shown in FIG. 4, the threshold voltage distributions are set in four areas. Two-bit memory states “11”, “10”, “01”, and “00” are allocated to these areas in this order. The data “11” represents the data erasing state. The rest of the data “10”, “01”, and “00” represent the data programming state.
In this case, the ranges of threshold voltages for the two states of the data “10” and “01” need to be narrow, as the data of the other memory states are at both sides of these data. For example, when the data “10”, “01”, and “00” are programmed such that the corresponding threshold voltages exceed 4 V, 5 V, and 6 V, respectively, the threshold voltage distribution ranges of the data “10” and “01” need to be accommodated within ranges from 4 V to 4.35 V and from 5 V to 5.35 V, respectively. When the distribution ranges of threshold voltage are narrowed, a voltage difference between the adjacent ranges of threshold voltage becomes large, which expands the operation margin of the read operation and makes it possible to carry out a high-speed read operation. Therefore, in order to ensure reliable high-speed read operation, the distribution ranges of threshold voltages need to be adjusted to become as narrow as possible.
A general method of programming data into a multilevel flash memory is disclosed in, for example, Giovanni Campardo, et al., “40-mm2 3-V-Only 50-MHz 64-Mb 2-b/Cell CHE NOR Flash Memory”, IEEE Journal Of Solid-State Circuits, Vol. 35, No. 11, November 2000. Another method is disclosed in Japanese Unexamined Patent Publication No. 11-124879.
FIG. 16 is a flowchart of the conventional programming method to program the data “10” or “01”. When the program operation of programming the data “10” is started, a gate voltage Vg is set to an initial value Vg1 (for example, 5 V), and the gate voltage Vg is output from a word line voltage supply circuit. The gate voltage Vg is applied to the control gate of the memory cell via the word line. A voltage Vdp (for example, 5 V) is supplied to the bit line, and a programming pulse of the voltage Vdp is applied to the drain of the memory cell. Verification is carried out next. When it is decided that the threshold voltage in the memory cell is at 4 V or more, the programming pulse is not applied to this memory cell. Specifically, the bit line connected to the drain of the corresponding memory cell is set to a floating state during the application of the programming pulse to the other memory cells on the same word line. Alternatively, 0 V is applied to this bit line. On the other hand, when it is decided that the threshold voltage in the memory cell is not at 4 V or more, the programming pulse is applied to this memory cell again. At this reprogramming time, the gate voltage Vg applied to the control gate of the memory cells is set higher than the gate voltage Vg at the first programming time by a voltage step ΔVg (for example, 0.3 V), thereby to set Vg+ΔVg (=5.3 V) as a new gate voltage Vg. This gate voltage Vg (=5.3 V) is applied to the control gate of the memory cells via the word line from the word line voltage supply circuit. A voltage Vdp (for example, 5 V) that is the same as the voltage applied at the first time is supplied to the bit line, thereby applying a programming pulse of the voltage Vdp (for example, 5 V) to the drain of the memory cell. As a result, the threshold voltage of the memory cell increases. Verification is carried out again. When it is decided that the threshold voltage in the memory cell is at 4 V or more, the programming pulse is not applied to this memory cell. On the other hand, when it is decided that the threshold voltage in the memory cell is not 4 V or more, the gate voltage Vg applied to the control gate of the memory cell is set higher than the gate voltage Vg by a voltage step ΔVg (for example, 0.3 V). With this arrangement, Vg+ΔVg (=5.6 V) is set as a new gate voltage Vg. This gate voltage Vg (=5.6 V) is applied to the control gate of the memory cell via the word line from the word line voltage supply circuit. This reprogramming is repeated until when all the memory cells to be programmed on the same word line with data have a threshold voltage of 4 V or more. FIG. 17 is an illustration of a change in the gate voltage Vg in this case. FIG. 18 is an illustration of a change in the distribution range of threshold voltage. When a maximum change in the threshold voltage at one reprogramming is ΔVt, the threshold voltage in the memory cell to be reprogrammed with data is 4 V or less. Therefore, as shown in FIG. 18, by repeating the reprogramming, the lower limit of the distribution range of threshold voltage is gradually increased while maintaining the upper limit of the distribution range of threshold voltage at 4 V+ΔVt. With this arrangement, the distribution range of threshold voltage can be finally accommodated with the voltage range of ΔVt. In general, the change ΔVt in the threshold voltage at one reprogramming time is considered approximately equivalent to the voltage step ΔVg that is used at the reprogramming time. Therefore, the distribution range of threshold voltage is accommodated within the constant range by adjusting the voltage step ΔVg utilizing this characteristic. When a targeted width of the threshold voltage distribution is 0.35 V, for example, 0.3 V is used as the voltage step ΔVg.
As described above, in order to speed up the read operation (for example, in order to realize a flash memory having an access time of 80 ns or less), the distribution range of threshold voltage in the memory cell needs to be controlled to be as narrow as possible. In an “eight-level” flash memory that aims at a much lower cost, the distribution range of threshold voltage in the memory cell needs to be controlled narrower, as shown in the threshold voltage distribution in FIG. 19. The ΔVt is considered to be approximately equivalent to the increase ΔVg in the gate voltage Vg that is used at the reprogramming time. Therefore, when the conventional programming method is employed, at the time of accommodating the distribution range of threshold voltage finally into the voltage range of ΔVt, it is considered that the distribution range of threshold voltage can be controlled to be narrower by making smaller the voltage step ΔVg. However, the inventors of the present application find that the following problems occur when the voltage step ΔVg is simply made smaller using the conventional programming method. The present invention is made based on this finding.
FIG. 20 is an illustration of a change in the threshold voltage distribution of the memory state “10” of the four-level flash memory cell when the gate voltage Vg is increased by the voltage step ΔVg at each time of the application of a programming pulse. FIG. 20 is an illustration of a change in an upper limit value Vtmax and a lower limit value Vtmin of the threshold voltage distribution, which has a range of about 1000 mV in this example. In FIG. 20, a memory cell of which threshold voltage is 4 V or more as a result of the verification is not removed and is reprogrammed continuously. Therefore, both the upper limit value Vtmax and the lower limit value Vtmin increase in parallel. The gate voltage Vg at the time of the first application of the programming pulse is 5 V, and the increase ΔVg in the gate voltage Vg to be used at the reprogramming time is 0.05 V. As shown in FIG. 20, the Vtmax is 4 V and the Vtmin is 3 V at the time after the first application of the programming pulse. The Vtmax is 4.2 V and the Vtmin is 3.2 V at the time after the second application of the programming pulse. The Vtmax is 4.35 V and the Vtmin is 3.35 V after the time of the third application of the programming pulse. The change ΔVt in the threshold voltage between the first and second programming times is 0.2V, and the change ΔVt in the threshold voltage between the second and third programming times is 0.15V. It is clear that this change in the threshold voltage is larger than the 0.05 V of the voltage step ΔVg. In other words, even when the increase ΔVg in the gate voltage Vg is made smaller, the change ΔVt in the threshold voltage does not become smaller following this reduction in ΔVg. As shown in FIG. 20, ΔVt is larger than ΔVg even after a number of programming pulses. As a result, according to the conventional programming method, an “over-programming” that exceeds a predetermined threshold voltage range could occur.
FIG. 21 is an illustration of an error (ΔVt−ΔVg) between the threshold voltage change ΔVt between the programming pulses and the voltage step ΔVg, for ΔVg of 0.05 V, 0.1 V, 0.15 V, 0.2 V, and 0.3 V. The error (ΔVt−ΔVg) represents a level of the “over-programming”. In FIG. 21, the vertical axis represents the error (ΔVt−ΔVg) and the horizontal axis represents the pulse number of two consecutive programming pulse between which the errors (ΔVt−ΔVg) are measured. As shown in FIG. 21, after the second application of the programming pulse, the “over-programming” of 0.15 V occurs at the voltage step ΔVg of 0.05 V, and the “over-programming” of 0.12 V occurs at the voltage step ΔVg of 0.1 V. It is clear that the “over-programming” level is larger when the voltage step ΔVg is smaller. It is also clear that the “over-programming” is mitigated when the number of programming pulse increases.